module Multicycle_Processor(iClk, iReset, Start
,iMemInstructionWriteMode, iMemAddress, iMemWriteData  //Added to write instructions to memory
,oInst0 ,oData1, oData2, oData5, oData16, oData17 //added for test
);
input iClk, iReset, Start;


//Added to write instructions to memory
input iMemInstructionWriteMode;
input [31:0] iMemAddress, iMemWriteData;

output [31:0] oInst0, oData1, oData2, oData5, oData16, oData17; //for test

wire [31:0] Instruction;

wire PCWriteCond;	// PC
wire PCWrite;	// PC
wire IorD;		// Selector of Mux between PC and Memory
wire MemRead;	// Read Enable of Memory
wire MemWrite;	// Write Enable of Memory
wire MemtoReg;	// Selector of Mux between MemoryDataRegister and Regusters 
wire IRWrite;	// Write Enable of InstructionRegister
wire RegDst;		// Selector of Mux between InstructionRegister and Regusters 
wire RegWrite;	// Write Enable of Registers
wire ALUSrcA;	// Selector of Mux between A and ALU
wire [1:0]ALUSrcB;	// Selector of Mux between B and ALU 
wire [2:0]ALUOp;	// ALUOp
wire [1:0]PCSource;	// Selector of Mux between ALU and PC


Control U_Control(
.Start(Start),
.iOpcode(Instruction[31:26]),
.iFunction(Instruction[5:0]),
.iReset(iReset),
.iClk(iClk),
.oPCWriteCond(PCWriteCond),
.oPCWrite(PCWrite),
.oIorD(IorD),
.oMemRead(MemRead),
.oMemWrite(MemWrite),
.oMemtoReg(MemtoReg),
.oIRWrite(IRWrite),
.oRegDst(RegDst),
.oRegWrite(RegWrite),
.oALUSrcA(ALUSrcA),
.oALUSrcB(ALUSrcB),
.oALUOp(ALUOp),
.oPCSource(PCSource)
);

Datapath U_Datapath( 
.iClk(iClk), 
.iReset(iReset), 
.iPCWriteCond(PCWriteCond), 
.iPCWrite(PCWrite), 
.iIorD(IorD), 
.iMemRead(MemRead), 
.iMemWrite(MemWrite), 
.iIRWrite(IRWrite), 
.iRegDst(RegDst), 
.iMemtoReg(MemtoReg), 
.iRegWrite(RegWrite), 
.iALUSrcA(ALUSrcA), 
.iALUOp(ALUOp), 
.iALUSrcB(ALUSrcB), 
.iPCSource(PCSource), 
.oInstruction(Instruction),

//Added to write instructions to memory
.iMemInstructionWriteMode(iMemInstructionWriteMode), 
.iMemAddress(iMemAddress), 
.iMemWriteData(iMemWriteData)

, .oInst0(oInst0), .oData1(oData1), .oData2(oData2), .oData5(oData5), .oData16(oData16), .oData17(oData17) //for test
);


endmodule